HBM4 has over 2048 signals to the processor’s PHY with tight signal integrity requirements that require the HBM stack to be < 0.5 mm from the processor die. That’s why HBM integration is done with interposers (soldered on the package). So, it’d be the CPU package that integrates it. Motherboard is too far away.
Kind of seems like we should be making chips with both. Big HBM stack on top as a sort of huge L5 cache like thing. And then a bunch of DRAM type sockets (like LPCAMM) around the exterior.
For chips with integrated CPU+GPU+NPU, it could be worth it tech-wise. The GPU and NPU can eat HBM bandwidth. For general purpose CPU code, the HBM would likely not be worth it. It's high bandwidth, but you trade latency, and general CPU code is branchy. Economics-wise, the HBM stacks alone will cost more than a consumer CPU (or APU).
[edit] The packaging needed to support HBM is also much more expensive too. If demand for current HBM applications tanks and the manufacturing lines need filled, then maybe. Currently, the price point would make it very very niche.
Hobbyist electronics manufacturing has always been reasonably affordable, with the old perfboard / stripboard from RadioShack having been a staple of the hobby since forever. At-home etching was also available for the people who cared more about having cool PCBs than about having healthy lungs.
The availability of cheap factory-made low-volume PCBs goes hand-in-hand with the switch towards smaller and smaller SMD parts. You don't need a professional PCB for a few THT parts, and you can always put the odd SOT part on a breakout or dead-bug solder it. But when many interesting parts started to become available only in QFN/DFN (or worse: BGA) packages, proper PCBs became the only option. Combine that with PCB factories wanting to make a few extra bucks off of their wasted board space, and it is suddenly quite attractive to hack together a quick-and-dirty ordering page for hobbyists and prototypes. No new technology needed, just a new market waiting to be served.
$4 / die custom chips are indeed very attractive, but the $4000 MOQ is not. A high-school or college student just getting into electronics can afford spending $100 on a hobby project just to discover it is broken, but there is no way they can afford spending "used car" money on it. That's startup territory, or "retired Bay Area engineer" territory.
Unfortunately they still run into the same basic economic problems: a wafer might be only $1000, but a set of masks is closer to $100k. This means you want to maximize the number of wafers, with ideally each wafer only containing a single copy of each chip. But even if you assume they just fill a reticle to the absolute maximum with unique chips (let's call it 40 unique designs) and fit, say, only 25 copies on a wafer, that's still only 40 wafers, so $2500/wafer in one-off costs - completely dwarfing the actual wafer itself.
For hobbyists you want a process closer to $10k / wafer with zero mask costs. Fit the same 1000 chips on there as before, and you can now sell people 5 copies of their chip for $50. That's a completely different game!
The terms to search for are fan-out wafer level packaging (FOWLP) and TSMC InFO. The chiplets come from different wafers and are reconstituted into a molded plastic wafer, allowing multiple die side-by-side. Then multiple layers of wires are built on top, terminating in a BGA.
Ok, part of my confusion was that it was being presented in contrast to InFO-oS and InFO-PoP, but it appears to mostly be a modified version of InFO-PoP called InFO-M? Because Apple has been using InFO-PoP for almost a decade at this point, starting with the A10.
Apple has not shipped an InFO-PoP with side-by-side integrated die yet. This is expected to be the first one, using RDLs for the die-to-die interconnect (so different than M-Ultra series that uses silicon bridges).
Equipment for ion implantation already includes mini accelerators [1] [2]. The semiconductor equipment industry in general has many machines that feel like they came out of a physics lab into a semi fab. For example, plasma dry-etching or deep-reactive ion etching. EUV litho is just one of many very interesting problems--currently the bottleneck so it's talked about a lot.
You also need hundreds of other machines from Applied Materials, KLA Tencor, Lam Research, Tokyo Electron, etc. Then, years of process development R&D: what temperature do we bake this layer at, how long, what profile, what atmosphere in the tool… Every process step has a large parameter set to optimize. Creating a process is a painstaking many many variable optimization slog.
Just wanted to add that since I see people only mention ASML often here. They are very important, but there is so much more to TSMC’s success.
You are absolutely correct that design costs swamp mask costs by far. For 7 nm, it costs more than $271 million for design alone (EDA, verification, synthesis, layout, sign-off, etc) [1], and that’s a cheaper one. Industry reports say $650-810 million for a big 5 nm chip.
Keep in mind, a semiconductor fab has hundreds of other machines and equipment involved, and US companies are some of the biggest suppliers (Applied Materials, Lam Research, KLA-Tencor--all multi-billion dollar companies).
Lithography is definitely key, but all the equipment and process must work together.
