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awesome! keep up the great work!


There is a page[0] in the Bluesky docs on this, though it effectively boils down to “fetch each user repository”.

[0] https://docs.bsky.app/docs/advanced-guides/backfill


Good suggestion. I think that my pre-race fueling strategy was better than previous races, but certainly lots of room for further improvement!


I think your insecurity about your race plan is from lack of confidence in your ability to run the full 26.2 miles at a given sub-3 hour pace.

Looking at your Strava workouts, your long runs were at a much slower than marathon pace, and very few of those runs were over 16 miles.

If you want to run the full 26.2 mile marathon at, say, 6:45/mile pace, then you should be able to run 22 or 20 miles, averaging 6:45/mile.

You can start at a shorter distance, say 12-16mi at a slower pace, and work up to 20mi+ at or close to race pace.

You can play around with planning a race plan with these race simulation workouts, i.e. all miles at race pace or half distance at race pace+5secs, last half at race pace-5secs, etc.

Also check into marathon training plans for ideas of how to progress and schedule workouts until race day.


I appreciate the kind words! Best of luck on your leap of faith -- it takes courage to attempt it in the first place!


Luke (author of Hazard3) provided some context regarding including the Hazard3 cores alongside the M33's:

> I can't compare the sizes of the two cores. The final die size would likely have been exactly the same with the Hazard3 removed, as std cell logic is compressible, and there is some rounding on the die dimensions due to constraints on the pad ring design. I can say that we taped out at a very high std cell utilisation and we might have saved a few grey hairs during final layout and STA by deleting the RISC-V cores.

https://x.com/wren6991/status/1821582405188350417


I actually recently interviewed one of the folks (Philip Freidin) who worked on the 29k.

Clip of Philip describing AMD 29k: https://youtu.be/I5cYxLg7Vfc

Full Episode: https://microarch.club/episodes/1/

Previous HN Post: https://news.ycombinator.com/item?id=39452960


I'll grab that one too, thanks!


Detailed show notes with timestamps and links can be found here: https://microarch.club/episodes/11/


There is a pretty wide range of setups, but you can get started with just a laptop and Open Broadcaster Studio (OBS) streaming to YouTube or Twitch. My personal setup has evolved a bit, and currently consists of:

- Two machines. One is for development and the other is dedicated streaming.

- The development machine is connected to the streaming machine with an HDMI cable and an Elgato capture card.

- Microphone is a Rode Podcaster (XLR), which is connected to an audio interface.

- Audio interface is a Scarlett 2i2, which is attached to the streaming machine via USB.

- Currently just using the webcam on the streaming machine, which is terrible, but no one is there to see my face anyway :)

Best of luck on your streaming journey and feel free to reach out if I can help out in any way!


I could not agree more with this recommendation. For folks who don't yet have this book but are interested, there is a set of online companion materials[0] that are freely available and contain a good bit of useful information.

[0] https://www.elsevier.com/books-and-journals/book-companion/9...


Author here -- thanks for the feedback! This is a quick post that is focused on how to logically think about the circuit, but I agree that all of the attributes you enumerated are valuable information as well. I plan to continue diving deeper in future posts. I am currently posting every Friday as part of my goal of gaining a deep understanding of chip design[0]. Please feel free to continue to provide feedback on future posts as well!

[0]: https://danielmangum.com/posts/a-three-year-bet-on-chip-desi...


I think the article is fine but what you're really driving towards is the idea of synchronous design, and how that simplifies design and analysis. Some of the objections here might go away if it were framed that way.


That's a great point. Thanks for the feedback!


I liked the post. as a novice with fpgas and hdls, I find posts like this very approachable. Refreshing tbh


Perhaps showing the synthesized gates and how say a structural version of the code will synthesize would explain in more detail


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