My experience at a big defense contractor was like that. Huge spectrum of work. Fortunately I got to work on some very cool cutting edge (at the time) technology. We were developing wafer scale integration, doing things like inter-reticle stitching to make chips the size of an entire 4 inch wafer (4 inch wafers were common at the time). Through on-chip redundancy/self-testing/configuration we were getting 50% yield. It was pretty amazing. But so many other engineers were using stone-aged technology to field satellite systems, working under hugely bloated management structures where easily 20% of your time was spent reporting and accounting for hours and costs. For quite a few years I was clever enough or lucky enough to avoid ever having to work one of those dinosaur projects.
My god, the latency on a wafer sized die must have been incredible. Certainly such a beast wouldn't be used for logic... A 4 inch image sensor would be quite interesting though.
It was indeed logic. A pair of MACs, a pair of ALUs, big chunk of on-chip memory and a big ol' mess of wires to interconnect them all. Heavily pipelined. For use in signal processing applications where latency wasn't really a concern.
We dabbled with big image sensor arrays but the sparing for yield was messy and we never came to grips with how to deal with the situation where the working sensors were in random locations in the array. It seemed to really mess up all the important systems level calculations. We also never completely worked out testing. The big logic chip had BILBO blocks so we could just put it in self test mode, run a lot of clock cycles, check the signatures, and switch in the working blocks. The sensor array needed more than that. Perhaps solvable issues, but we never got around to it.
