The job of a gate is to "hold open" / "pinch closed" a channel with an electric field. The closer to the gate, the better the hold/pinch. In ye olde days, you'd slap a gate on the top of a channel and call it a day. Every part of the channel was close enough to the gate get a good pinch.
Then everything shrunk and smaller channels wound up needing stronger pinches to completely shut them off. Instead of slapping a gate on top and calling it a day, they raised the channel into a fin and drizzled the gate over 3 sides so that it could pinch from the left and right, not just the top. Those are FinFETs.
The next step is to have the gate on the bottom, too, so that it can pinch from all four sides. The channel literally goes through the gate, which surrounds it on all sides. Those are Gate-All-Around FETs, or GAAFETs.
This is beautifully written; I stepped away from keeping up an in-depth understanding of silicon processing a bit before FinFETs took over and this feels like one of the best introductions to the basics of gate geometry of FETs.
I never quite got how electrostatic control was supposed to work with GAA, Fin and derivatives: without the bulk, how is your electric field supposed to work?
Unless the Gate itself is hollow, and the "bulk" is in the middle, like air would be in a hollow spaghetti? Or tha you use way higher voltages for the gate than for the drain/source (but then, how do you drive that?). I guess I just need to look it up, but most presentations gloss over that part.
Can you elaborate for us uninitiated? Why GAAFET might help Samsung win at 3nm?