Oh, transistors haven't shrunk that much. I don't know the exact process details, but integration density has been going up( putting gates vertical with FinFET), together with better electrostatic control (GAAFET, kind of a step uf from FDSOI), while gate length remains the same.
Think about it this way: you're doping semiconductors by adding a few other atoms. On the order of 1 dopant atom per 1M intrinsic (undopped) semiconductor. How thin can you make it before there's only a dozen dopant atoms? And then, how do you make sure they are evenly distributed? And in the same way across multiple transistors, to guarantee a consistent performance? Yield is key, at this scale.
Technically, they can still improve density by embracing 3D. A friend of mine works on multi-gate vertical nanowire transistors, for instance, but that's still a few years (or a decade?) away from the fab.
Think about it this way: you're doping semiconductors by adding a few other atoms. On the order of 1 dopant atom per 1M intrinsic (undopped) semiconductor. How thin can you make it before there's only a dozen dopant atoms? And then, how do you make sure they are evenly distributed? And in the same way across multiple transistors, to guarantee a consistent performance? Yield is key, at this scale.
Technically, they can still improve density by embracing 3D. A friend of mine works on multi-gate vertical nanowire transistors, for instance, but that's still a few years (or a decade?) away from the fab.