FPGAs just have a much lower essential complexity.
Adding one undocumented latch is enough to undermine an ASIC CPU. To do that to an FPGA, you'd have to know where the layout engine is putting the circuit you intend to pwn, and good luck with that staying still under any revision.
If this did become a problem, a technique analogous to memory randomization could be employed to make any given kernel unique from the hardware's perspective.
Adding one undocumented latch is enough to undermine an ASIC CPU. To do that to an FPGA, you'd have to know where the layout engine is putting the circuit you intend to pwn, and good luck with that staying still under any revision.
If this did become a problem, a technique analogous to memory randomization could be employed to make any given kernel unique from the hardware's perspective.