It's a standardised "process" sizing established by the International Technology Roadmap for Semiconductors. Originally they did correspond to actual feature sizes but since around 1997, they no longer correlate to actual sizes and are more just a marketing term that matches the same naming scheme as previously.
Occassionally a given process will correspond to actual sizes but it's more out of luck than anything else.
This isn't fully correct. Drawn 7nm is like 20nm, but effective gate length is shorter due to short channel effects. So, this numbers are almost 1-to-1 reflection of effective gate length. People mix up the transistor pitch with gate length. We can make small gate length devices but diffusion (source/drain) and contacts don't shrink as much, so we end up having a larger area needed for these.
Occassionally a given process will correspond to actual sizes but it's more out of luck than anything else.