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Rochus
on Aug 11, 2024
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Hazard3: 3-stage RV32IMACZb* processor with debug
But if they do formal verification, then at least SV assertions should be present; will talke another look at the code.
wren6991
on Aug 13, 2024
[–]
Yosys supports very basic SVA (immediate assert/assume, $past etc) in addition to Verilog 2005
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